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max186/max188 low-power, 8-channel, serial 12-bit adcs for pricing, delivery, and ordering information, plea se contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.m aximintegrated.com. evaluation kit available general description the max186/max188 are 12-bit data-acquisition sys-tems that combine an 8-channel multiplexer, high- bandwidth track/hold, and serial interface together with high conversion speed and ultra-low power consump- tion. the devices operate with a single +5v supply or dual ?v supplies. the analog inputs are software con- figurable for unipolar/bipolar and single-ended/differen- tial operation. the 4-wire serial interface directly connects to spi, qspi and microwire devices without external logic. a serial strobe output allows direct connection totms320 family digital signal processors. the max186/max188 use either the internal clock or an external serial-interface clock to perform successive- approximation a/d conversions. the serial interface can operate beyond 4mhz when the internal clock is used. the max186 has an internal 4.096v reference while the max188 requires an external reference. both parts have a reference-buffer amplifier that simplifies gain trim . the max186/max188 provide a hard-wired shdn pin and two software-selectable power-down modes.accessing the serial interface automatically powers up the devices, and the quick turn-on time allows the max186/max188 to be shut down between every con- version. using this technique of powering down between conversions, supply current can be cut to under 10? at reduced sampling rates. the max186/max188 are available in 20-pin pdip and so packages, and in a shrink small-outline package (ssop), that occupies 30% less area than an 8-pin pdip. for applications that call for a parallel interface, see the max180/max181 data sheet. for anti-aliasing filters, consult the max274/max275 data sheet. ________________________applications portable data loggingdata-acquisition high-accuracy process control automatic testing robotics battery-powered instruments medical instruments ____________________________features ? 8-channel single-ended or 4-channel differential inputs ? single +5v or 5v operation ? low power: 1.5ma (operating mode) 2 a (power-down mode) ? internal track/hold, 133khz sampling rate ? internal 4.096v reference (max186) ? spi-/qspi-/microwire-/tms320-compatible 4-wire serial interface ? software-configurable unipolar or bipolar inputs ? 20-pin pdip, so, ssop packages ? evaluation kit available ordering information 2019 18 17 16 15 14 13 12 11 12 3 4 5 6 7 8 9 10 top view pdip/so/ssop v dd sclkcs din sstrbdout dgnd agnd refadjvref shdn v ss ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 max186max188 + ____________________ pin configuration qspi is a trademark of motorola. microwire is a registered trademark of national semiconductor. 19-0123; rev 5; 1/12 ordering information continued on last page. ? parts are offered in grades a, b, c and d (grades defined in electrical characteristics). when ordering, please specify grade. contact factory for availability of a-grade in ssop package. * dice are specified at +25?, dc parameters only. + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max186 _cpp+ 0c to +70c 20 pdip max186_cwp+ 0c to +70c 20 so max186_cap+ 0c to +70c 20 ssop max186dc/d 0c to +70c dice* max186_epp+ -40c to +85c 20 pdip max186_ewp+ -40c to +85c 20 so max186_eap+ -40c to +85c 20 ssop downloaded from: http:///
relative accuracy (note 2) low-power, 8-channel, serial 12-bit adcs 2 maxim integrated max186/max188 absolute maximum ratings electrical characteristics (v dd = 5v ?%; v ss = 0v or -5v; f clk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max186 4.7? capacitor at vref pin; max188?xternal reference, vref = 4.096v applied to vref pin; t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol min typ max units ?.0 lsb ?.75 ?.0 ?.5 differential nonlinearity dnl ? lsb ?.0 ?.0 ?.0 resolution 12 bits ?.5 offset error ?.0 lsb ?.0 ?.5 ?.0 ?.0 gain error (note 3) ?.0 lsb gain temperature coefficient ?.8 ppm/? ?.1 lsb sinad 70 db thd -80 db spurious-free dynamic range sfdr 80 db channel-to-channel crosstalk -85 db conditions max186d/max188d max186d/max188d max186 (all grades) max188c max186c max186b/max188b no missing codes over temperature max186a/max188a max186b/max188b max186c/max188c external reference4.096v (max188) external reference, 4.096v max186a/max188a 65khz, v in = 4.096v p-p (note 4) v dd to agnd............................................................-0.3v to +6v v ss to agnd ............................................................+0.3v to -6v v dd to v ss ..............................................................-0.3v to +12v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7 to agnd, dgnd .............(v ss - 0.3v) to (v dd + 0.3v) ch0?h7 total input current...........................................?0ma vref to agnd ...........................................-0.3v to (v dd + 0.3v) refadj to agnd.......................................-0.3v to (v dd + 0.3v) digital inputs to dgnd...............................-0.3v to (v dd + 0.3v) digital outputs to dgnd ............................-0.3v to (v dd + 0.3v) digital output sink current .................................................25ma continuous power dissipation (ta = +70?) pdip (derate 11.11mw/? above +70?) .....................889mw so (derate 10.00mw/? above +70?) ........................800mw ssop (derate 8.00mw/? above +70?) .....................640mw operating temperature ranges max186_c/max188_c ........................................0? to +70? max186_e/max188_e......................................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? max188a max188b max188c max188d channel-to-channel offset matching signal-to-noise + distortion ratio total harmonic distortion(up to the 5th harmonic) dc accuracy (note 1) dynamic specifications (10khz sine wave input, 4.096v p-p , 133ksps, 2.0mhz external clock, bipolar input mode) downloaded from: http:///
external clock frequency range low-power, 8-channel, serial 12-bit adcs maxim integrated 3 max186/max188 parameter symbol conditions min typ max units small-signal bandwidth -3db rolloff 4.5 mhz full-power bandwidth 800 khz internal clock 5.5 10 conversion time (note 5) t conv external clock, 2mhz, 12 clocks/conversion 6 ? track/hold acquisition time t az 1.5 ? aperture delay 10 ns aperture jitter <50 ps internal clock frequency 1.7 mhz electrical characteristics (continued) (v dd = 5v ?%; v ss = 0v or -5v; f clk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max186 4.7? capacitor at vref pin; max188?xternal reference, vref = 4.096v applied to vref pin; t a = t min to t max , unless otherwise noted.) external compensation, 4.7? 0.1 2.0 internal compensation (note 6) 0.1 0.4 used for data transfer only 10 mhz unipolar, v ss = 0v input voltage range, single-ended and differential (note 9) bipolar, v ss = -5v v multiplexer leakage current on/off leakage current, v in = ?v ?.01 ? ? input capacitance (note 6) 16 pf vref output voltage t a = +25? 4.076 4.096 4.116 v vref short-circuit current 30 ma max186a, max186b,max186c ?0 ?0 ?0 ?0 vref tempco max186d ?0 load regulation (note 7) 0 to 0.5ma output load 2.5 internal compensation 0 capacitive bypass at vref external compensation 4.7 ? internal compensation 0.01 capacitive bypass at refadj external compensation 0.01 ? max186_c max186_e refadj adjustment range ?.5 % ?ref/2 0 to vref input voltage range v input current 200 350 ? input resistance 12 20 k shutdown vref input current 1.5 10 ? buffer disable threshold refadj v dd - 50mv v v dd + 2.50 50mv conversion rate analog input internal reference (max186 only, reference buffer enabled) external reference at vref (buffer disabled, vref = 4.096v) ppm/? mv downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs 4 maxim integrated max186/max188 electrical characteristics (continued) (v dd = 5v ?%; v ss = 0v or -5v; f clk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max186 4.7? capacitor at vref pin; max188?xternal reference, vref = 4.096v applied to vref pin; t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max internal compensation mode 0 ? capacitive bypass at vref external compensation mode 4.7 max186 1.678 v/v max188 1.638 max186 ?0 ? refadj input current max188 ? v inh 2.4 v v inl 0.8 v din, sclk, cs input hysteresis v hyst 0.15 v din, sclk, cs input leakage i in v in = 0v or v dd ? ? c in (note 6) 15 pf shdn input high voltage v inh v dd - 0.5 v shdn input low voltage v inl 0.5 v shdn input current, high i inh v shdn = v dd 4.0 ? shdn input current, low i inl v shdn = 0v -4.0 ? shdn input mid voltage v im v shdn voltage, open v flt v shdn = open 2.75 v v shdn = open -100 100 na i sink = 5ma 0.4 output voltage low v ol i sink = 16ma 0.3 v output voltage high v oh i source = 1ma 4 v three-state leakage current i l v cs = 5v ?0 ? three-state output capacitance c out v cs = 5v (note 6) 15 pf positive supply voltage v dd 5 ?% v din, sclk, cs input capacitance shdn max allowed leakage, mid input negative supply voltage v ss 0 or -5 ?% v operating mode 1.5 2.5 fast power-down 30 70 positive supply current i dd full power-down 21 0 operating mode and fast power-down 50 negative supply current i ss full power-down 10 ? ma ? din, sclk, cs input low voltage din, sclk, cs input high voltage 1.5 v dd -1.5 digital inputs (din, sclk, c c s s , s s h h d d n n ) digital outputs (dout, sstrb) power requirements units external reference at refadj reference-buffer gain downloaded from: http:///
c load = 100pf 20 150 sclk fall to output data valid t do max18_ _c/e note 1: tested at v dd = 5.0v; v ss = 0v; unipolar input mode. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range hasbeen calibrated. note 3: max186 ?internal reference, offset nulled; max188 ?external reference (vref = +4.096v), offset nulled. note 4: ground on-channel; sine wave applied to all off channels. note 5: conversion time defined as the number of clock cycles times the clock period; clock has 50% duty cycle. note 6: guaranteed by design. not subject to production testing. note 7: external load should not change during conversion for specified accuracy. note 8: measured at v supply +5% and v supply -5% only. note 9: the common-mode range for the analog inputs is from v ss to v dd . low-power, 8-channel, serial 12-bit adcs maxim integrated 5 max186/max188 parameter symbol conditions units positive supply rejection (note 8) psr ?.06 ?.5 mv negative supply rejection(note 8) psr v ss = -5v ?%; external reference, 4.096v; full-scale input ?.01 ?.5 mv electrical characteristics (continued) (v dd = 5v ?%; v ss = 0v or -5v; f clk = 2.0mhz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); max186 4.7? capacitor at vref pin; max188?xternal reference, vref = 4.096v applied to vref pin; t a = t min to t max , unless otherwise noted.) timing characteristics (v dd = 5v ?%; v ss =0v or -5v, t a = t min to t max , unless otherwise noted.) parameter symbol conditions units sclk pulse width low t cl 200 ns sclk fall to sstrb t sstrb c load = 100pf 200 ns t sdv external clock mode only, c load = 100pf 200 ns t str external clock mode only, c load = 100pf 200 ns t sck internal clock mode only 0 ns acquisition time t az 1.5 ? din to sclk setup t ds 100 ns din to sclk hold t dh 0 ns ns cs fall to output enable t dv c load = 100pf 100 ns cs rise to output disable t tr c load = 100pf 100 ns cs to sclk rise setup t css 100 ns cs to sclk rise hold t csh 0 ns sclk pulse width high t ch 200 ns sstrb rise to sclk rise (note 6) cs fall to sstrb output enable (note 6) v dd = 5v ?%; external reference, 4.096v; full-scale input min typ max min typ max cs rise to sstrb output disable (note 6) downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs 6 maxim integrated max186/max188 low-power, 8-channel, serial 12-bit adcs __________________________________________typical operating characteristics 0.30 -0.05 -60 140 power-supply rejection vs. temperature 0.00 0.25 temperature (?) psr (lsbs) 60 0.100.05 -40 20 100 0.15 0.20 -20 0 40 80 120 v dd = +5v ?% v ss = 0v or -5v 2.456 internal reference voltage vs. temperature 2.452 2.455 temperature (?) vrefadj (v) 2.4542.453 -40 -20 0 20 40 60 80 100 120 0.16 0 -60 -20 60 140 channel-to-channel offset matching vs. temperature 0.02 0.12 temperature (?) offset matching (lsbs) 20 100 0.100.04 -40 0 40 80 120 0.140.08 0.06 20 -140 0 66.5khz max186/max188 fft plot ?133khz -120 0 -80 -100 -40 -20 -60 ft = 10khzfs = 133khz 33.25khz amplitude (db) frequency f t = 10khz f s = 133khz t a = +25? _____________________________________________________________pin description pin name function 1C8 ch0Cch7 sampling analog inputs 9 v ss negative supply voltage. connect to -5v 5% or agnd 10 shdn three-level shutdown input. pulling shdn low shuts the max186/max188 down to 10a (max) supply current, otherwise the max186/max188 are fully operational. p ulling shdn high puts the reference-buffer amplifier in internal compensation mode. leav ing shdn unconnected puts the reference-buffer amplifier in external compensation mode. 11 vref reference voltage for analog-to-digital conversion. also, output of the r eference buffer amplifier (4.096v in the max186, 1.638 x refadj in the max188). add a 4.7 f capacitor to ground when using external compensation mode. also functions as an input when used wi th a precision external downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs maxim integrated 7 max186/max188 +5v 3k c load dgnd dout c load dgnd 3k dout a. high-z to v oh and v ol to v oh b. high-z to v ol and v oh to v ol +5v 3k c load dgnd dout c load dgnd 3k dout a v oh to high-z b v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disabled time input shift register control logic int clock output shift register +2.46v reference (max186) t/h analog input mux 12-bit sar adc in doutsstrb v dd dgndv ss sclk din ch0ch1 ch3 ch2ch7 ch6 ch5 ch4 agnd refadj vref out ref clock +4.096v 20k 1.65 12 3 4 5 6 7 8 1011 12 13 1516 17 1819 max186max188 cs shdn a 20 149 figure 3. block diagram ________________________________________________pin description (continued) pin name function 12 refadj input to the reference-buffer amplifier. to disable the reference-buffer amplifi er, connect refadj to v dd . 13 agnd analog ground. also in- input for single-ended conversions. 14 dgnd digital ground 15 dout serial data output. data is clocked out at the falling edge of sclk . high impedance when cs is high. 16 sstrb serial strobe output. in internal clock mode, sstrb goes low when the max186/max188 begin the a/d conversion and goes high when the conversion is done. in external clock mode , sstrb pulses high for one clock period before the msb decision. high impedance whe n cs is high (external mode). 17 din serial data input. data is clocked in at the rising edge of sclk. 18 cs active-low chip select. data will not be clocked into din unless cs is low. when cs is high, dout is high impedance. 19 sclk serial clock input. clocks data in and out of serial interface. in external clock mode, sclk also sets the conversion speed. (duty cycle must be 40% to 60% in external clock mode.) 20 v dd positive supply voltage, +5v 5% downloaded from: http:///
_______________detailed description the max186/max188 use a successive-approximationconversion technique and input track/hold (t/h) circuit- ry to convert an analog signal to a 12-bit digital output. a flexible serial interface provides easy interface to microprocessors. no external hold capacitors are required. figure 3 shows the block diagram for the max186/max188. pseudo-differential input the sampling architecture of the adc? analog com-parator is illustrated in the equivalent input circuit (figure 4). in single-ended mode, in+ is internally switched to ch0-ch7 and in- is switched to agnd. in differential mode, in+ and in- are selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5 and ch6/ch7. configure the channels with table 3 and table 4. in differential mode, in- and in+ are internally switched to either one of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain sta- ble within ?.5lsb (?.1lsb for best results) with respect to agnd during a conversion. accomplish this by connecting a 0.1? capacitor from ain- (the select- ed analog input, respectively) to agnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans three sclk cycles and endson the falling sclk edge after the last bit of the input control word has been entered. at the end of the acqui- sition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex-er switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is sim- ply agnd. this unbalances node zero at the input of the comparator. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a charge of 16pf x [(v in +) - (v in -)] from c hold to the binary-weighted capacitive dac, which in turn forms a digital represen-tation of the analog input signal. track/hold the t/h enters its tracking mode on the falling clockedge after the fifth bit of the 8-bit control word has been shifted in. the t/h enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. if the converter is set up for single-ended inputs, in- is connected to agnd, and the converter samples the ??input. if the converter is set up for differential inputs, in- connects to the ? input, and the difference of | in+ - in- | is sampled. at the end of the conversion, the positive input connectsback to in+, and c hold charges to the input signal. the time required for the t/h to acquire an input signalis a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. acquisition time is cal- culated by: t az = 9 x (r s + r in ) x 16pf, where r in = 5k , r s = the source impedance of the input signal, and t az is never less than 1.5?. note that source impedances below 5k do not significantly affect the ac performance of the adc. higher sourceimpedances can be used if an input capacitor is con- nected to the analog inputs, as shown in figure 5. note that the input capacitor forms an rc filter with the input source impedance, limiting the adc? signal bandwidth. input bandwidth the adc? input tracking circuitry has a 4.5mhzsmall-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic sig- nals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. low-power, 8-channel, serial 12-bit adcs 8 maxim integrated max186/max188 ch0 ch1 ch2ch3 ch4ch5 ch6 ch7 agnd c switch track t/h switch 10k r s c hold hold 12-bit capacitive dac vref zero comparator ? + 16pf single-ended mode: in+ = cho-ch7, in? = agnd.differential mode: in+ and in? selected from pairs of ch0/ch1, ch2/ch3, ch4/ch5, ch6/ch7. at the sampling instant,the mux input switches from the selected in+ channel to the selected in? channel. input mux figure 4. equivalent input circuit downloaded from: http:///
full scale v refadj x a* analog input range and input protection internal protection diodes, which clamp the analoginput to v dd and v ss , allow the channel input pins to swing from v ss - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, theinputs must not exceed v dd by more than 50mv, or be lower than v ss by 50mv. if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off-channels over two milliamperes, as excessive current will degrade the conversion accuracy of the on-channel. the full-scale input voltage depends on the voltage at vref. see tables 1a and 1b. quick look to evaluate the analog performance of themax186/max188 quickly, use the circuit of figure 5. the max186/max188 require a control byte to be writ- ten to din before each conversion. tying din to +5v feeds in control bytes of $ff (hex), which trigger low-power, 8-channel, serial 12-bit adcs maxim integrated 9 max186/max188 reference zero scale full scale internal reference(max186 only) 0v +4.096v 0v at vref 0v vref external reference at refadj reference negative full scale zero scale internal reference(max186 only) -4.096v/2 0v external reference at refadj -1/2v refadj x a* 0v at vref -1/2 vref 0v +4.096v/2 +1/2v refadj x a* +1/2 vref 0.1? v dd dgnd agnd v ss cs sclk din dout sstrb shdn +5v n.c. 0.01? ch7 refadj vref c2 0.01? +2.5v reference c14.7? d1 1n4148 +5v 0v to 4.096v analog input +2.5v ** oscilloscope ch1 ch2 ch3 ch4 * full-scale analog input, conversion result = $fff (hex)**required for max188 only. a potentiometer may be used in place of the reference for test purposes. max186max188 +5v 2mhz oscillator sclk sstrb dout* figure 5. quick-look circuit * a = 1.678 for the max186, 1.638 for the max188 table 1b. bipolar full scale, zero scale, and negative full scale table 1a. unipolar full scale and zero scale * a = 1.678 for the max186, 1.638 for the max188 downloaded from: http:///
single-ended unipolar conversions on ch7 in externalclock mode without powering down between conver- sions. in external clock mode, the sstrb output pulses high for one clock period before the most significant bit of the 12-bit conversion result comes out of dout. varying the analog input to ch7 should alter the sequence of bits from dout. a total of 15 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on the falling edge of sclk. how to start a conversion a conversion is started on the max186/max188 byclocking a control byte into din. each rising edge on sclk, with cs low, clocks a bit from din into the max186/max188? internal shift register. after cs falls, the first arriving logic ??bit defines the msb of thecontrol byte. until this first ?tart?bit arrives, any num- ber of logic ??bits can be clocked into din with no effect. table 2 shows the control-byte format. the max186/max188 are fully compatible withmicrowire and spi devices. for spi, select the correct clock polarity and sampling edge in the spi control reg- isters: set cpol = 0 and cpha = 0. microwire and spi both transmit a byte and receive a byte at the same time. using the typical operating circuit , the simplest software interface requires only three 8-bit transfers toperform a conversion (one 8-bit transfer to configure the adc, and two more 8-bit transfers to clock out the 12-bit conversion result). example: simple software interface make sure the cpu? serial interface runs in mastermode so the cpu generates the serial clock. choose a clock frequency from 100khz to 2mhz. 1) set up the control byte for external clock mode, call it tb1. tb1 should be of the format: 1xxxxx11binary, where the xs denote the particular channel and conversion-mode selected. low-power, 8-channel, serial 12-bit adcs 10 maxim integrated max186/max188 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 bit name description 7(msb) start the first logic 1 ?bit after cs goes low defines the beginning of the control byte. 6 sel2 these three bits select which of the eight channels are used for the conversion. 5 sel1 see tables 3 and 4. 4 sel0 3 uni/ bip 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode. in unipolar mode, an analog input signal from 0v to vref can be converted; in bipolar mode, the signal can range from -vref/2 to +vref/2. 2 sgl/ dif 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single-ended mode, input signal voltages are referred to agnd. in differential mode,the voltage difference between two channels is measured. see tables 3 and 4. 1 pd1 selects clock and power-down modes. 0(lsb) pd0 pd1 pd0 mode 00 full power-down (i q = 2?) 01 fast power-down (i q = 30?) 10 internal clock mode 1 1 external clock mode table 2. control-byte format downloaded from: http:///
2) use a general-purpose i/o line on the cpu to pull cs on the max186/max188 low. 3) transmit tb1 and simultaneously receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and simulta- neously receive byte rb3. 6) pull cs on the max186/max188 high. figure 6 shows the timing for this sequence. bytes rb2and rb3 will contain the result of the conversion padded with one leading zero and three trailing zeros. the total conversion time is a function of the serial clock frequency and the amount of dead time between 8-bit transfers. make sure that the total conversion time does not exceed 120?, to avoid excessive t/h droop. digital output in unipolar input mode, the output is straight binary(see figure 15). for bipolar inputs, the output is twos-complement (see figure 16). data is clocked out at the falling edge of sclk in msb-first format. low-power, 8-channel, serial 12-bit adcs maxim integrated 11 max186/max188 sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 agnd 00 0 + 10 0 + 00 1 + 10 1 + 01 0 + 11 0 + 01 1 + 11 1 + table 3. channel selection in single-ended mode (sgl/ d d i i f f f f = 1) sel2 sel1 sel0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 00 0 + 00 1 + 01 0 + 01 1 + 10 0 + 10 1 + 11 0 + 11 1 ? table 4. channel selection in differential mode (sgl/ d d i i f f f f = 0) downloaded from: http:///
internal and external clock modes the max186/max188 may use either an external serialclock or the internal clock to perform the successive-approximation conversion. in both clock modes, the external clock shifts data in and out of the max186/max188. the t/h acquires the input signal as the last three bits of the control byte are clocked into din. bits pd1 and pd0 of the control byte program the clock mode. figures 7 through 10 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital con- version steps. sstrb pulses high for one clock periodafter the last bit of the control byte. successive-approxi- mation bit decisions are made and appear at dout on each of the next 12 sclk falling edges (see figure 6). sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb will output a logic low. figure 8 shows the sstrb timing inexternal clock mode. the conversion must complete in some minimum time, or else droop on the sample-and-hold capacitors may degrade conversion results. use internal clock mode if the clock period exceeds 10?, or if serial-clock interruptions could cause the conversion interval to exceed 120?. low-power, 8-channel, serial 12-bit adcs 12 maxim integrated max186/max188 sstrb cs sclk din dout 14 8 1 2 1 6 2 0 2 4 start sel2 sel1 sel0 uni/ bip scl/ diff pd1 pd0 b11 msb b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 lsb acquisition 1.5 s (clk = 2mhz) idle filled with zeros idle conversion t acq a/d state rb1 rb2 rb3 ? ? ? ? ? ? ? ? ? ? ? ? cs sclk din dout t csh t css t cl t ds t dh t dv t ch t do t tr t csh figure 6. 24-bit external clock mode conversion timing (spi, qspi and microwire compatible) figure 7. detailed serial-interface timing downloaded from: http:///
internal clock in internal clock mode, the max186/max188 generatetheir own conversion clock internally. this frees the microprocessor from the burden of running the sar con- version clock, and allows the conversion results to be read back at the processor? convenience, at any clock rate from zero to typically 10mhz. sstrb goes low at the start of the conversion and then goes high when the con- version is complete. sstrb will be low for a maximum of 10?, during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out at this register at any time after the conversion is com- plete. after sstrb goes high, the next falling clock edge will produce the msb of the conversion at dout, fol-lowed by the remaining bits in msb-first format (see figure 9). cs does not need to be held low once a con- version is started. pulling cs high prevents data from being clocked into the max186/max188 and three-states dout, but it does not adversely effect an internal clock-mode conversion already in progress. when inter- nal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 10 shows the sstrb timing in internal clockmode. in internal clock mode, data can be shifted in and out of the max186/max188 at clock rates exceeding 4.0mhz, provided that the minimum acquisition time, t az , is kept above 1.5?. low-power, 8-channel, serial 12-bit adcs maxim integrated 13 max186/max188 ? ? ? ? ? ? ? ? ? ? ? ? t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb ? ? ? ? ? ? ? ? sstrb cs sclk din dout 14 8 12 18 20 24 start sel2 sel1 sel0 uni/ dip scl/ diff pd1 pd0 b11 msb b10 b9 b2 b1 b0 lsb acquisition 1.5 s (clk = 2mhz) idle filled with zeros idle conversion 10 s max a/d state 2 3 5 6 7 9 10 11 19 21 22 23 t conv figure 8. external clock mode sstrb detailed timing figure 9. internal clock mode timing downloaded from: http:///
data framing the falling edge of cs does not start a conversion on the max186/max188. the first logic high clocked into din isinterpreted as a start bit and defines the first bit of the control byte. a conversion starts on the falling edge of sclk, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any- time the converter is idle, e.g. after v cc is applied. or the first high bit clocked into din after bit 5 of aconversion in progress is clocked onto the dout pin. if a falling edge on cs forces a start bit before bit 5 (b5) becomes available, then the current conversionwill be terminated and a new one started. thus, the fastest the max186/max188 can run is 15 clocks per conversion. figure 11a shows the serial-interface timing necessary to perform a conversion every 15 sclk cycles in external clock mode. if cs is low and sclk is continuous, guarantee a start bit by first clocking in 16zeros. most microcontrollers require that conversions occur in multiples of 8 sclk clocks; 16 clocks per conversion will typically be the fastest that a microcontroller can drive the max186/max188. figure 11b shows the serial-interface timing necessary to perform a conver- sion every 16 sclk cycles in external clock mode. __________ applications information power-on reset when power is first applied and if shdn is not pulled low, internal power-on reset circuitry will activate themax186/max188 in internal clock mode, ready to con- vert with sstrb = high. after the power supplies have been stabilized, the internal reset time is 100? and no conversions should be performed during this phase. sstrb is high on power-up and, if cs is low, the first logical 1 on din will be interpreted as a start bit. until aconversion takes place, dout will shift out zeros. reference-buffer compensation in addition to its shutdown function, the shdn pin also selects internal or external compensation. the compen-sation affects both power-up time and maximum conver- sion speed. compensated or not, the minimum clock rate is 100khz due to droop on the sample-and-hold. to select external compensation, open shdn . see the typical operating circuit , which uses a 4.7? capacitor at vref. a value of 4.7? or greater ensures stability andallows operation of the converter at the full clock speed of 2mhz. external compensation increases power-up time (see the choosing power-down mode section, and table 5). internal compensation requires no external capacitor atvref, and is selected by pulling shdn high. internal com- pensation allows for shortest power-up times, but is onlyavailable using an external clock and reduces the maxi- mum clock rate to 400khz. low-power, 8-channel, serial 12-bit adcs 14 maxim integrated max186/max188 pd0 clock in t sstrb t csh t conv t sck sstrb ? ? ? sclk ? ? ? t css note: for best noise performance, keep sclk low during conversion. cs ? ? ? figure 10. internal clock mode sstrb detailed timing downloaded from: http:///
power-down choosing power-down mode you can save power by placing the converter in alow-current shutdown state between conversions. select full power-down or fast power-down mode via bits 7 and 8 of the din control byte with shdn high or open (see tables 2 and 6). pull shdn low at any time to shut down the converter completely. shdn overrides bits 7 and 8 of din word (see table 7).full power-down mode turns off all chip functions that draw quiescent current, reducing i dd and i ss typically to 2?. fast power-down mode turns off all circuitry except thebandgap reference. with the fast power-down mode, the supply current is 30?. power-up time can be shortened to 5? in internal compensation mode. in both software shutdown modes, the serial interface remains operational, however, the adc will not convert. table 5 illustrates how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. in external compensation mode, the power-up time is 20ms with a 4.7? compensation capacitor (200ms with a 33? capacitor) when the capacitor is fully discharged. in fast power-down, you can eliminate start-up time by using low-leakage capacitors that will not dischargemore than 1/2lsb while shut down. in shutdown, the capacitor has to supply the current into the reference (1.5? typ) and the transient currents at power-up. figures 12a and 12b illustrate the various power-down sequences in both external and internal clock modes. software power-down software power-down is activated using bits pd1 andpd0 of the control byte. as shown in table 6, pd1 and pd0 also specify the clock mode. when software shut- down is asserted, the adc will continue to operate in the last specified clock mode until the conversion is complete. then the adc powers down into a low quies- cent-current state. in internal clock mode, the interface remains active and conversion results may be clocked out while the max186/max188 have already entered a software power-down. the first logical 1 on din will be interpreted as a start bit, and powers up the max186/max188. following the start bit, the data input word or control byte also deter- mines clock and power-down modes. for example, if the din word contains pd1 = 1, then the chip will remain powered up. if pd1 = 0, a power-down will resume after one conversion. low-power, 8-channel, serial 12-bit adcs maxim integrated 15 max186/max188 sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 conversion result 1 sstrb b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 control byte 2 s 1 8181 cs sclk din dout s control byte 0 control byte 1 s conversion result 0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b11 b10 b9 b8 conversion result 1 ? ? ? ? ? ? ? ? ?? ? ? figure 11a. external clock mode, 15 clocks/conversion timing figure 11b. external clock mode, 16 clocks/conversion timing downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs 16 maxim integrated max186/max188 reference reference- vref power- power-up maximum buffer buffer capacitor down delay sampling compensation (f) mode (s) rate (ksps) mode enabled internal fast 5 26 enabled internal full 300 26 enabled external 4.7 fast see figure 14c 133 enabled external 4.7 full see figure 14c 133 disabled fast 2 133 disabled full 2 133 table 5. typical power-up delay times pd1 pd0 device mode 1 1 external clock mode 1 0 internal clock mode 0 1 fast power-down mode 0 0 full power-down mode s s h h d d n n device reference-buffer state mode compensation 1 enabled internal compensation open enabled external compensation 0 full power-down n/a table 6. software shutdown and clock mode table 7. hard-wired shutdown and compensation mode powered up full power down powered up powered up data valid (12 data bits) data valid (12 data bits) data invalid valid external external internal sx xxxx 11 s 01 xx xx x xx xxx s1 1 fast power-down mode dout din clock mode shdn sets externalclock mode sets external clock mode sets fastpower-down mode figure 12a. timing diagram power-down modes, external clock downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs maxim integrated 17 max186/max188 full power-down powered up powered up data valid data valid internal clock mode sx xxxx 10 s 00 xx xxx s mode dout din clock mode sets internalclock mode sets fullpower-down conversion conversion sstrb 10 0 din refadj vref 2.5v 0v4v 0v 10 1 1 1 110 0 10 1 fullpd fastpd nopd fullpd fastpd 2ms wait complete conversion sequence t buffen 15? = rc = 20k x c refadj (zeros) ch1 ch7 (zeros) hardware power-down the shdn pin places the converter into the full power-down mode. unlike with the software shut-downmodes, conversion is not completed. it stops coinci- dentally with shdn being brought low. there is no power-up delay if an external reference is used and isnot shut down. the shdn pin also selects internal or external reference compensation (see table 7). power-down sequencing the max186/max188 auto power-down modes cansave considerable power when operating at less than maximum sample rates. the following discussion illus- trates the various power-down sequences. lowest power at up to 500 conversions/channel/second the following examples illustrate two different power-downsequences. other combinations of clock rates, compen- sation modes, and power-down modes may give lowest power consumption in other applications. figure 14a depicts the max186 power consumption for one or eight channel conversions utilizing full power-down mode and internal reference compensation. a 0.01? bypass capacitor at refadj forms an rc filter with the internal 20k reference resistor with a 0.2ms time constant. to achieve full 12-bit accuracy, 10 timeconstants or 2ms are required after power-up. waiting 2ms in fastpd mode instead of full power-up will reduce the power consumption by a factor of 10 or more. this is achieved by using the sequence shown in figure 13. figure 12b. timing diagram power-down modes, internal clock figure 13. max186 fullpd/fastpd power-up sequence downloaded from: http:///
lowest power at higher throughputs figure 14b shows the power consumption withexternal-reference compensation in fast power-down, with one and eight channels converted. the external 4.7? compensation requires a 50? wait after power-up, accomplished by 75 idle clocks after a dummy conver- sion. this circuit combines fast multi-channel conversion with lowest power consumption possible. full power-down mode may provide increased power sav- ings in applications where the max186/max188 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. external and internal references the max186 can be used with an internal or externalreference, whereas an external reference is required for the max188. diode d1 shown in the typical operating circuit ensures correct start-up. any standard signal diode can be used. for both parts, an external refer-ence can either be connected directly at the vref ter- minal or at the refadj pin. an internal buffer is designed to provide 4.096v at vref for both the max186 and max188. the max186? internally trimmed 2.46v reference is buffered with a gain of 1.678. the max188's buffer is trimmed with a buffer gain of 1.638 to scale an external 2.5v reference at refadj to 4.096v at vref. max186 internal reference the full-scale range of the max186 with internal referenceis 4.096v with unipolar inputs, and ?.048v with bipolar inputs. the internal reference voltage is adjustable to ?.5% with the reference-adjust circuit of figure 17. external reference with both the max186 and max188, an external refer-ence can be placed at either the input (refadj) or the output (vref) of the internal buffer amplifier. the refadj input impedance is typically 20k for the max186 and higher than 100k for the max188, where the internal reference is omitted. at vref, the inputimpedance is a minimum of 12k for dc currents. during conversion, an external reference at vref mustbe able to deliver up to 350? dc load current and have an output impedance of 10 or less. if the reference has higher output impedance or is noisy, bypass it close tothe vref pin with a 4.7? capacitor. low-power, 8-channel, serial 12-bit adcs 18 maxim integrated max186/max188 1000 1 0 100 300 500 max186 full power-down 10 100 max186-14a conversions per channel per second 200 400 2ms fastpd wait400khz external clock internal compensation 50 150 250 350 450 8 channels 1 channel avg. supply current (?) 10,000 10 0 max186/max188 fast power-down 100 1000 conversions per channel per second 2k 8 channels 1 channel 4k 6k 8k 10k 12k 14k 16k 18k 2mhz external clockexternal compensation 50? wait avg. supply current (?) figure 14a. max186 supply current vs. sample rate/second, fullpd, 400khz clock figure 14b. max186/max188 supply current vs. sample rate/second, fastpd, 2mhz clock 3.02.5 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 time in shutdown (sec) power-up delay (ms) figure 14c. typical power-up delay vs. time in shutdown downloaded from: http:///
using the buffered refadj input avoids externalbuffering of the reference. to use the direct vref input, disable the internal buffer by tying refadj to v dd . transfer function and gain adjust figure 15 depicts the nominal, unipolar input/output(i/o) transfer function, and figure 16 shows the bipolar input/output transfer function. code transitions occur halfway between successive integer lsb values. output coding is binary with 1 lsb = 1.00mv (4.096v/4096) for unipolar operation and 1 lsb = 1.00mv ((4.096v/2 - -4.096v/2)/4096) for bipolar operation. figure 17, the max186 reference-adjust circuit, shows how to adjust the adc gain in applications that use the internal reference. the circuit provides ?.5% (?5lsbs) of gain adjustment range. layout, grounding, bypassing for best performance, use printed circuit boards.wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 18 shows the recommended system ground connections. a single-point analog ground (?tar ground point) should be established at agnd, sepa- rate from the logic ground. all other analog grounds and dgnd should be connected to this ground. noother digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low imped- ance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the high-speed comparator in the adc. bypassthese supplies to the single-point analog ground with 0.1? and 4.7? bypass capacitors close to the max186/max188. minimize capacitor lead lengths for best supply-noise rejection. if the +5v power supply is very noisy, a 10 resistor can be connected as a low- pass filter, as shown in figure 18. low-power, 8-channel, serial 12-bit adcs maxim integrated 19 max186/max188 output code full-scale transition 11 . . . 11111 . . . 110 11 . . . 101 00 . . . 01100 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2lsb fs = +4.096v 1lsb = fs 4096 input voltage (lsbs) 011 . . . 111011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001 100 . . . 000 -fs 0v input voltage (lsbs) +fs - 1lsb fs = +4.096 2 1lsb = +4.096 4096 +5v 510k 100k 24k 0.01 f 12 refadj max186 figure 17. max186 reference-adjust circuit figure 15. max186/max188 unipolar transfer function, 4.096v = full scale figure 16. max186/max188 bipolar transfer function, ?.096v/2 = full scale downloaded from: http:///
high-speed digital interfacing with qspi the max186/max188 can interface with qspi at highthroughput rates using the circuit in figure 19. this qspi circuit can be programmed to do a conversion on each of the eight channels. the result is stored in mem- ory without taxing the cpu since qspi incorporates its own micro-sequencer. figure 19 depicts the max186, but the same circuit could be used with the max188 by adding an external reference to vref and connecting refadj to v dd . figure 20 details the code that sets up qspi forautonomous operation. in external clock mode, the max186/max188 perform a single-ended, unipolar con- version on each of their eight analog input channels. figure 21, qspi assembly-code timing, shows the tim- ing associated with the assembly code of figure 20. the first byte clocked into the max186/max188 is the control byte, which triggers the first conversion on ch0. the last two bytes clocked into the max186/max188 are all zero and clock out the results of the ch7 conversion. low-power, 8-channel, serial 12-bit adcs 20 maxim integrated max186/max188 +5v -5v gnd supplies dgnd +5v dgnd v ss agnd v dd digital circuitry max186/max188 r* = 10 * optional figure 18. power-supply grounding connection 2019 18 17 16 15 14 13 12 11 23 4 5 6 7 8 9 10 max186 ch0 +ch1 ch2 ch3 ch4 ch5 ch6 ch7 v ss shdn v dd sclk cs din sstrb dout dgnd agnd refadj vref v ddi , v dde , v ddsyn , v stby sckpcs0 mosi miso * clock connections not shown v ssi vsse mc68hc16 0.1 f 4.7 f 0.01 f 0.1 f 4.7 f analog inputs +5v + 1 figure 19. max186 qspi connection downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs maxim integrated 21 max186/max188 *title : max186.asm* description : * this is a shell program for using a stand-alone 68hc16 without any external memory. the internal 1k ram * is put into bank $0f to maintain 68hc11 code compatibility. this program was written with software * provided in the motorola 68hc16 evaluation kit. * * roger j.a. chen, applications engineer * maxim integrated products * november 20, 1992 * ****************************************************************************************************************************************************** include ?quates.asm? ;equates for common reg addrsinclude ?rg00000.asm? ;initialize reset vector include ?rg00008.asm? ;initialize interrupt vectors org $0200 ;start program after interrupt vectors include ?nitsys.asm ;set ek=f,xk=0,yk=0,zk=0 ;set sys clock at 16.78 mhz, cop off include ?nitram.asm? ;turn on internal sram at $10000 ;set stack (sk=1, sp=03fe) main: jsr initqspi mainloop: jsr read186 wait: ldaa spsranda #$80 beq wait ;wait for qspi to finish bra mainloop endprogram:initqspi: ;this routine sets up the qspi microsequencer to operate on its own. ;the sequencer will read all eight channels of a max186/max188 each time ;it is triggered. the a/d converter results will be left in the ;receive data ram. each 16 bit receive data ram location will ;have a leading zero, 12 bits of conversion result and three zeros. ; ;receive ram bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ;a/d result 0 msb lsb 0 0 0 ***** initialize the qspi registers ****** pshapshb ldaa #%01111000 staa qpdr ;idle state for pcs0-3 = high ldaa #%01111011 staa qpar ;assign port d to be qspi ldaa #%01111110 staa qddr ;only miso is an input ldd #$8008 std spcr0 ;master mode,16 bits/transfer, ;cpol=cpha=0,1mhz ser clock ldd #$0000 std spcr1 ;set delay between pcs0 and sck, figure 20. max186/max188 assembly-code listing downloaded from: http:///
;set delay between transfers ldd #$0800std spcr2 ;set endqp to $8 for 9 transfers ***** initialize qspi command ram ***** ldaa #$80 ;cont=1,bitse=0,dt=0,dsck=0,pcs0=activestaa $fd40 ;store first byte in command ram ldaa #$c0 ;cont=1,bitse=1,dt=0,dsck=0,pcs0=active staa $fd41 staa $fd42 staa $fd43 staa $fd44 staa $fd45 staa $fd46 staa $fd47 ldaa #$40 ;cont=0,bitse=1,dt=0,dsck=0,pcs0=active staa $fd48 ***** initialize qspi transmit ram ***** ldd #$008f std $fd20 ldd #$00cf std $fd22 ldd #$009f std $fd24 ldd #$00df std $fd26 ldd #$00af std $fd28 ldd #$00ef std $fd2a ldd #$00bf std $fd2c ldd #$00ff std $fd2e ldd #$0000 std $fd30 pulbpula rts read186:;this routine triggers the qspi microsequencer to autonomously ;trigger conversions on all 8 channels of the max186. each ;conversion result is stored in the receive data ram. pshaldaa #$80 oraa spcr1 staa spcr1 ;just set spe pula rts ***** interrupts/exceptions ***** bdm: bgnd ;exception vectors point here ;and put the user in background debug mode low-power, 8-channel, serial 12-bit adcs 22 maxim integrated max186/max188 figure 20. max186/max188 assembly-code listing (continued) downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs maxim integrated 23 max186/max188 tms320c3x to max186 interface figure 22 shows an application circuit to interface themax186/max188 to the tms320 in external clock mode. the timing diagram for this interface circuit is shown in figure 23. use the following steps to initiate a conversion in the max186/max188 and to read the results: 1) the tms320 should be configured with clkx (trans- mit clock) as an active-high output clock and clkr(tms320 receive clock) as an active-high input clock. clkx and clkr of the tms320 are connected together with the sclk input of the max186/max188. 2) the max186/max188 cs is driven low by the xf_ i/o port of the tms320 to enable data to be clockedinto din of the max186/max188. 3) an 8-bit word (1xxxxx11) should be written to the max186/max188 to initiate a conversion and placethe device into external clock mode. refer to table 2 to select the proper xxxxx bit values for your spe- cific application. 4) the sstrb output of the max186/max188 is moni- tored via the fsr input of the tms320. a fallingedge on the sstrb output indicates that the conver- sion is in progress and data is ready to be received from the max186/max188. xf clkxclkr dxdr fsr cssclk din dout sstrb tms320c3x max186max188 figure 22. max186/max188 to tms320 serial interface ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cssclk sstrb din figure 21. qspi assembly-code timing 5) the tms320 reads in one data bit on each of the next 16 rising edges of sclk. these data bits rep-resent the 12-bit conversion result followed by four trailing bits, which should be ignored. 6) pull cs high to disable the max186/max188 until the next conversion is initiated. downloaded from: http:///
low-power, 8-channel, serial 12-bit adcs 24 maxim integrated max186/max188 _ordering information (continued) cs sclk din sstrb dout start sel2 sel1 sel0 uni/bip sgl/dif pd1 pd0 msb b10 b1 lsb highimpedance highimpedance figure 23. tms320 serial interface timing diagram chip information substrate connected to v dd v dd i/o sck (sk)*mosi (so) miso (si) v ss shdn sstrb dout din sclk cs v ss agnd dgnd v dd refadj ch7 c3 0.1 f c4 0.1 f ch0 +5v c2 0.01 f 0v to 4.096v analog inputs max186 cpu c14.7 f vref __________typical operating circuit ? parts are offered in grades a, b, c and d (grades defined in electrical characteristics). when ordering, please specify grade. contact factory for availability of a-grade in ssop package. * dice are specified at +25?, dc parameters only. + denotes a lead(pb)-free/rohs-compliant package. part temp range pin-package max188 _cpp+ 0c to +70c 20 pdip max188_cwp+ 0c to +70c 20 so max188_cap+ 0c to +70c 20 ssop max188dc/d 0c to +70c dice* max188_epp+ -40c to +85c 20 pdip max188_ewp+ -40c to +85c 20 so max188_eap+ -40c to +85c 20 ssop part temp range board type max186evkit-dip 0c to +70c through-hole package information for the latest package outline information and land patterns (foot-prints), go to www.maximintegrated.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 pdip p20+3 21-0043 20 so w20+3 21-0042 91-0108 20 ssop a20+1 21-0056 91-0094 downloaded from: http:///
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 25 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. low-power, 8-channel, serial 12-bit adcs max186/max188 revision history revision number revision date description pages changed 0 3/93 initial release 5 1/12 updated the ordering informaion and elecrical characerisics . 1, 3, 18 downloaded from: http:///

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